Project2024

32-bit RISC-V Arithmetic Logic Unit for IoT chips

A 32-bit Arithmetic Logic Unit built for RISC-V IoT chips, taken from Verilog through OpenLane’s open-source ASIC flow to a fabricatable GDSII layout on the Sky130 process.

Where the ALU sits inside a RISC-V processor, alongside the register file, decode logic and program counter.

Standard-cell placement for the top-level design, viewed in Graal after OpenROAD placement.

OpenROAD's routing log — design-rule errors driven to zero across six iterations.

The finished GDSII layout in KLayout, ready for fabrication — every transistor, via and routed wire.

Close-up of the metal-layer routing between standard cells.

Overview

Final-year project at Dedan Kimathi University of Technology, built with Peter Maina and supervised by Dr. Waweru Njeri at the Centre for Robotics and Biomedical Engineering’s IC Design Centre.

Most open-source RISC-V cores borrow their ALU from a larger, general-purpose design. This project went the other way: build a 32-bit ALU specifically for IoT and embedded workloads, open enough to study, modify and take all the way to a real chip layout — not just simulate.

What it does

The ALU covers the operations a RISC-V core actually needs plus a few IoT-relevant extras: addition, subtraction, integer and fixed-point (Q16.16) multiplication, division, left/right shifts, left/right rotates, bitwise AND/OR/XOR/NOT, min/max comparison, and load/store. The 32×32 multiplier uses a carry-save adder tree with a Kogge-Stone prefix adder for the final summation — parallel addition of the partial products instead of a slow ripple-carry chain.

From Verilog to silicon

Every operation was written as its own Verilog module (adder, multiplier, shifter, comparator, divider, memory) and driven by dedicated testbenches before being wired into the top-level ALU. Once the functional simulation matched expected output for every operation, the design went through OpenLane, the open-source ASIC flow built on OpenROAD, Yosys, Magic, Netgen and KLayout: logic synthesis, floorplanning, placement, clock and power distribution, routing, and signoff checks (timing, DRC, LVS), targeting SkyWater’s open-source Sky130 130nm process. The output is a real GDSII layout — the same file format used to fabricate an actual chip.

What I did

Wrote the ALU's Verilog modules: adder, subtractor, integer and fixed-point (Q16.16) multiplier, divider, shifter, rotator, comparator, bitwise units, and load/store
Built a 32-bit carry-save adder tree with a Kogge-Stone prefix adder for the multiplier, to parallelize partial-product summation
Wrote testbenches and simulated every operation, verifying decimal and hex output against expected results
Synthesized the design to a gate-level netlist with Yosys
Ran floorplanning, placement and routing through OpenLane/OpenROAD, targeting the SkyWater Sky130 PDK
Verified timing, wirelength and design-rule checks through OpenROAD's signoff flow until DRC errors reached zero
Generated the final GDSII layout and inspected the transistor, metal and via layers in KLayout

Tools & skills

Verilog HDL
RISC-V Architecture
OpenLane
OpenROAD
Yosys
SkyWater Sky130 PDK
ASIC Physical Design
Digital Logic Design
KLayout